Attacks on the HF Physical Layer of Contactless and RFID Systems

International audienceno abstrac

MATRICES DE DETECTEURS BOLOMETRIQUES POUR L'IMAGERIE DANS LES BANDES MILLIMETRIQUES (FAISABILITE, PERFORMANCES ET REALISATION D'UN DEMONSTRATEUR)

GRENOBLE1-BU Sciences (384212103) / SudocSudocFranceF

Participation au dépistage du cancer colorectal par le test Hémoccult II® (étude sur la population cible dans l'Hérault)

MONTPELLIER-BU Médecine UPM (341722108) / SudocMONTPELLIER-BU Médecine (341722104) / SudocPARIS-BIUM (751062103) / SudocSudocFranceF

Insertion of random delay with context-aware dummy instructions generator in a RISC-V processor

International audienc

SecDec: Secure Decode Stage thanks to masking of instructions with the generated signals

International audienc

SecDec: Secure Decode Stage thanks to masking of instructions with the generated signals

International audienc

Insertion of random delay with context-aware dummy instructions generator in a RISC-V processor

International audienc

Lightweight instruction-level encryption for embedded processors using stream ciphers

Over the last 30 years, a number of secure processor architectures have been proposed to protect software integrity and confidentiality during its distribution and execution. In such architectures, encryption (together with integrity checking) is used extensively, on any data leaving a defined secure boundary. In this paper, we show how encryption can be achieved at the instruction level using a stream cipher. Thus encryption is more lightweight and efficient, and is maintained deeper in the memory hierarchy than the natural off-chip boundaries considered in most research works. It requires the control flow graph to be used and modified as part of the off-line encryption process, but thanks to the LLVM framework, it can be integrated easily in a compiler pipeline, and be completely transparent to the programmer. We also describe hardware modifications needed to support this encryption method, the latter were added to a 32-bit MIPS soft core. The synthesis performed on a Altera Cyclone V FPGA shows that encryption requires 26% of extra logic, while slowing-down execution time by an average of 48% in the best setting. (C) 2018 Elsevier B.V. All rights reserved

Lightweight Software Encryption for Embedded Processors

International audienceOver the last 30 years, a number of secure processor architectures have been proposed to protect software integrity and confidentiality during its distribution and execution. In such architectures, encryption (together with integrity checking) is used extensively, on any data leaving a defined secure boundary. In this paper, we show how encryption can be achieved at the instruction level using a stream cipher. Thus encryption is more lightweight and efficient, and is maintained deeper in the memory hierarchy than the natural off-chip boundary considered in most research works. It requires the control flow graph to be used and modified as part of the off-line encryption process, but thanks to the LLVM framework, it can be integrated easily in a compiler pipeline, and be completely transparent to the programmer. We also describe hardware modifications needed to support this encryption method, the latter were added to a 32 bit MIPS soft core. The synthesis performed on a Altera Cyclone V FPGA shows that encryption requires 26% of extra logic, while slowingdown execution time by an average of 48% in the best setting